By Ashwini Sakharkar 7 Nov, 2024
Collected at: https://www.techexplorist.com/worlds-first-large-area-semiconductor-fabrication-with-tmdc/92015/
As the field of artificial intelligence (AI) continues to evolve, the urgent and growing need for next-generation high-performance semiconductors is increasing rapidly. To meet this demand, pioneering advancements in materials and innovative semiconductor structures have become essential.
For the first time worldwide, researchers have developed a 4-inch heterostructure fabrication technique utilizing plasma-enhanced chemical vapor deposition (PECVD). This innovation allows for the creation of low-power yet high-performance semiconductors, surpassing the limits of conventional silicon-based solutions.
The research team, led by Senior Researcher Hyeong-U Kim at the Semiconductor Manufacturing Research Center of the Korea Institute of Machinery and Materials (KIMM), in collaboration with Professor Taesung Kim’s team from the Department of Mechanical Engineering at Sungkyunkwan University, has made history. The team has successfully fabricated 4-inch heterostructure semiconductors using plasma technology for the first time in the world. This technology is expected to be utilized in AI semiconductors by leveraging next-generation semiconductor materials such as TMDc.
The research team has made this advancement using PECVD equipment to create two types of innovative 4-inch wafer-scale heterostructures. The first is a cutting-edge heterostructure combining WS₂ and graphene. This was achieved by depositing a mere 1-nanometer tungsten (W) metal layer onto a graphene-transferred wafer, followed by a precise H₂S plasma sulfurization process.
In addition, the team made a significant breakthrough in developing a metal-semiconductor heterostructure by integrating two distinct phases of molybdenum disulfide (MoS₂) as a thin film. The 1T phase, which exhibits a metastable orthorhombic structure, presents challenges for large-area wafer production compared to the stable hexagonal 2H phase.
However, the team successfully produced a 4-inch wafer in the 1T phase, paving the way for the implementation of the 1T-2H heterostructure. Conventional methods for creating heterostructures, like stacking, have been limited to small sizes (only a few micrometers) and often suffer from reproducibility issues.
The research team addressed these issues by utilizing PECVD to produce a 4-inch wafer-scale heterostructure. This innovation paves the way for the creation of a 3D integrated structure, which significantly diminishes power loss and heat dissipation, resulting in improved performance and energy efficiency—crucial elements for low-power, high-performance AI semiconductors.
“This newly developed technology not only fulfills wafer-size and reproducibility requirements but also allows experimental validation previously restricted to academic research,” KIMM’s Senior Researcher Hyeong-U Kim stated. “Using PECVD, a widely employed tool in the semiconductor industry, this technology offers high potential for mass production, likely contributing to advancements in AI semiconductor performance and commercialization.”
KIMM has obtained proprietary technology for the fabrication of two varieties of 4-inch heterostructure wafers by registering patents in the United States and South Korea.
Journal reference:
- Hyunho Seok, Minjun Kim, Jinill Cho, Sihoon Son, Yonas Tsegaye Megra, Jinhyoung Lee, Myeong Gyun Nam, Keon-Woo Kim, Kubra Aydin, Seong Soo Yoo, Hyeonjeong Lee, Vinit K. Kanade, Muyoung Kim, Jihun Mun, Jin Kon Kim, Ji Won Suk, Hyeong-U Kim, Pil J. Yoo, Taesung Kim. Electron Release via Internal Polarization Fields for Optimal S-H Bonding States. Advanced Materials, 2024; DOI: 10.1002/adma.202411211
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